1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor chips, and more particularly to a structure and novel methodology for forming solder bumps in Back-End-Of-Line (BEOL) semiconductor chip processing.
2. Description of the Prior Art
Controlled Collapse Chip Connection (C4) processes are well known in forming solder bumps in back-end-of line semiconductor fabrication, e.g., when chips are connected to their packaging. Typically, the formation of a C4 solder bump includes the conventional formation of a metallurgical system that includes the underlying final metal layer (pad), an Under Bump Metallurgy (UBM) and the solder ball. The UBM ideally should provide good adhesion to a wafer passivation and to the IC final metal pad, and, function as an effective solder diffusion barrier.
Current fabrication techniques implement Pb-free C4's using plating of the solder in a photoresist pattern, followed by wet etching of the UBM. In the prior art solder bump plating process, the UBM includes the deposition of an adhesion layer, e.g., a titanium-tungsten alloy (TiW), followed by wetting layers of Cr—Cu (chromium-copper alloy) and copper (Cu). The wetting layers ensure the solder completely covers the patterned Ti—W adhesion layer (thereby ensuring a large contact area between the solder ball and the chip, and providing high mechanical strength. In the solder bump plating process, the wafer is cleaned to remove oxides or organic residue prior to metal deposition and to roughen the wafer passivation and bond pad surface to promote better adhesion of the UBM. The UBM barrier layer metals such as TiW, Cr—Cu, and Cu may then be sequentially sputtered or evaporated over the entire wafer so that the UBM adheres to the wafer and passivation in addition to the bond pads. Next, a photoresist layer is applied and then metal layers (e.g., a Ni barrier layer followed by a Sn-based solder) are plated over the bond pad to a height as determined by the patterned photoresist. After the solder bump is formed, the photoresist is stripped, leaving the UBM exposed on the wafer. The UBM is subsequently removed from the wafer using a wet etch process (e.g., an H2O2-based wet etch).
As integrated circuits shrink in size, the pitch of the C4 solder bumps must also shrink. In the conventional C4 processing described, the barrier layer metals (typically TiW/CrCu/Cu) are wet etched after plating of the solder. Unfortunately, as C4 pitch decreases, the wet etch causes increasingly more undercut of the C4 solder bump (i.e., a greater percentage of area underneath the C4 is undercut), which degrades the mechanical reliability of the C4.
It would be highly desirable to provide a C4 fabrication technique that results in an improved C4 pitch and increases the mechanical stability of the formed solder bump.